1. Field of the Invention
The present invention relates generally to nanometer-scale lithography and more specifically to the formation of capacitors and other high density microelectronic devices having nanometer-scale trenches and vias.
2. Description of the Prior Art
The fabrication of dynamic RAMs (DRAMs) at the 64 Mb level and above is hampered by one's inability to fabricate capacitors which have sufficiently high capacitance. One solution is to increase the surface area of the capacitor without requiring more chip surface area. This is done by making deep trench cuts into the silicon (or GaAs) chip, with the trenches having a large depth-to-width ratio. After the trenches are cut, by Reactive Ion Etching (RIE), Orientation Dependent Etching (ODE), or other processing methods well known in the art, the entire exposed surface of the trench system is oxidized by known oxidation techniques, e.g. thermal wet oxidation or thermal dry oxidation. At this point the industry has experienced a severe problem. The surfaces of the oxidized trench system must be overlayed with a thin metal film to form the capacitor. Standard CVD processes are not very satisfactory.
In fabricating state-of-the-art ultra-large scale integrated (ULSI) microelectronic circuits in the microelectronics industry, e.g. in silicon or GaAs, one must make electrical contact from one metallization layer to another which are insulated from each other by insulating layers. In very complicated device structures, many layers of metallizations, insulation, and sometimes semiconductors are required. In more recent structures, e.g. those which will be developed in the next century, three-dimensional structures consisting of multiple layers will be fabricated. A significant difficulty with these new concepts, however, is making vertical electrical interconnections to the various metallization layers. The usual procedure is to etch a hole through a series of metallization and insulating layers, and stopping the etch as it reaches the desired metallization layer. The sides of the hole are then insulated and metallized to form the required conducting path. This metallization procedure is very hard to do with known techniques, particularly if the hole is extremely narrow, e.g. less than 1000 angstroms wide, with a large height-to-width ratio. That is, it is very hard to fabricate vias for ULSI devices. Furthermore, the hole etching process often forms non-parallel side walls which have either positive or negative slope. To make a fully conducting path, the metallization procedure must be very conformal and very uniform in thickness regardless of the shape or orientation of the surface it is put on.